1. Technical Field of the Invention
The present invention relates to a field programmable device (FPD) and in particular but not exclusively to Field Programmable Gate Arrays (FPGA).
2. Description of Related Art
Programmable gate arrays (PGA) have dramatically changed the process of designing digital hardware over the last few years. Unlike previous generations of digital electronic technology, where board level designs included large numbers of integrated circuits containing basic gates, virtually every digital design produced today consists mostly of high density integrated circuit devices. This is applied not only to custom devices such as processing units and memory, but also to solid state machines such as controllers, counters, registers and decoders.
When such circuits are destined for high volume systems they have been integrated into high density gate arrays, however for prototyping or other low volume situations many product designs are built using field programmable devices (FPD), one variant of which are known as field programmable gate arrays (FPGA). A field programmable device such as the FPGA is at its most basic level a series of configurable logic blocks (CLB), interconnected by a series of configurable connections or links, and read from and written to by a configurable input/output device.
The effectiveness of a field programmable device is the ability of the device to represent a required digital design, and be capable of being altered without the need for complete replacement. This ability is dependent on several factors such as device speed, and the complexity of design capable of being simulated. The complexity of the design is itself dependent on the complexity of the interconnections between the configurable logic blocks, and the number of the configurable logic blocks. The greater the number of blocks and the more complex the interconnection environment, the more complex the design that can be realised.
For any specified logic family and process technology on a fixed sized integrated circuit die, the most significant factor is the complexity or richness of the interconnections between the configurable logic blocks. In other words, for any given process technology where the speed and the size of the switching gate is fixed by practical limitations, and for a given integrated chip size FPD, a greater complexity of linkages can simulate a more complex digital circuit.
The interconnects in the field programmable device, unlike the logic blocks, are not subject to the same improvements in process technology with respect to improvements in feature sizes. Whereas the size of a logic block may be decreased as the size of the gate is decreased, the relative area taken by the interconnects remains the same, as reducing the width of the link increases the link resistance and therefore slows down the speed of the circuit. Reducing the distance between links increases the capacitive and inductive effects experienced between adjacent links which also slow down the circuit as well as increasing interference between links. Decreasing feature size may actually increase the relative area used by the interconnects as a greater number of configurable logic blocks can be introduced onto the same die size IC and therefore requiring a greater number of links not subject to the same reductions in size.
Interconnects are generally programmed, in the case of memory based FPDs, by a series of switching matrices controlled by memory latches. The memory latches create closed or open circuits between pairs of conducting lines. These configuration latches are supplied configuration data from a series of configuration registers and are enabled by an address register in a manner similar to the addressing and writing to a typical memory cell. The address and configuration data are passed to the configuration latches by a series of configuration and address lines. These lines have typically not been used for routing signals when the FPD is set into its active mode, and have been generally ignored as soon as the configuration of the gate array is completed.
This reflects an inefficient use of chip space. As these configuration and address lines are required to reach every switch matrix and configuration latch, they span most of the device area and occupy device area which could otherwise be used to provide interconnectivity between configurable logic blocks.
Solutions for implementing the use of configuration lines have been proposed. U.S. Pat. No. 6,037,800 describes a method for using shared signal lines for interconnection of logic elements and the configuration of a programmable gate array. During configuration of the gate array, the lines used to conduct the configuration signals can be heavily loaded and therefore the configuration is slow or requires more current to compensate for the high loading of the transmission path—with an associated increase in power drain and heat dissipation problem. A further problem associated with the method described in U.S. Pat. No. 6,037,800 is one of data contamination. Data on the data lines may be inadvertently transferred to the configuration line and vice versa.